Infrared (IR) detectors are often utilized to detect fires, overheating machinery, planes, vehicles, people, and any other objects that emit thermal radiation. Infrared detectors are unaffected by ambient light conditions or particulate matter in the air such as smoke or fog. Thus, infrared detectors have potential use in night vision and when poor vision conditions exist, such as when normal vision is obscured by smoke or fog. IR detectors are also used in non-imaging applications such as radiometers, gas detectors, and other IR sensors.
A variety of infrared detector types have been developed in the past. Many include a substrate having thereon a focal plane array (FPA), the focal plane array including a plurality of detector elements that each correspond to a respective pixel. The substrate contains an integrated circuit which is electrically coupled to the detector elements, and which is commonly known as a read out integrated circuit (ROIC).
Infrared detectors generally operate by detecting the differences in thermal radiance of various objects in a scene. That difference is converted into an electrical signal which is then processed. Microbolometers are infrared radiation detector elements that are fabricated on a substrate material using traditional integrated circuit fabrication techniques. Microbolometer detector arrays consist of thin, low thermal mass, thermally isolated, temperature-dependent resistive membrane structures. They are suspended over silicon ROIC wafers by long thermal isolation legs in a resonant absorbing quarter-wave cavity design.
Conventional infrared detector arrays and imagers operating at ambient temperature include microbolometer arrays made of thin films of hydrogenated amorphous silicon (a-Si:H) or amorphous vandium oxide (VOx). Other materials used for microbolometer arrays include films of various metal (e.g., titanium) and high temperature superconductors. For an array based on amorphous silicon, the detector pixel membrane is generally comprised of an ultra-thin (˜2000 Å) a-SiNx/a-Si:H/a-SiNx structure. The membrane is deposited at a low temperature nominally below 400° C using silane (SiH4) and ammonia (NH3) precursors for the amorphous silicon nitride (a-SiNx) layers, and using silane for the hydrogenated amorphous silicon (a-Si:H) layer. Hydrogen atoms from silane (SiH4) molecules are the source of hydrogen content in the a-Si:H layer. A thin absorbing metal layer such as Titanium (Ti), Titanium-Aluminum alloy (TiAl), Nichrome (NiCr), black gold, or other material absorbing in the infrared band of interest, (e.g., at wavelength range of 1 micron to 14 micron), is inserted in the membrane to enhance infrared absorptance. Contact between the a-Si:H detector electrodes and the interconnect pads on a complementary metal oxide semiconductor (CMOS) signal processor of the ROIC is accomplished by thick aluminum tab metal interconnects.
After fabrication, microbolometers are generally placed in vacuum packages to provide an optimal environment for the sensing device. Conventional microbolometers measure the change in resistance of a detector element after the microbolometer is exposed to thermal radiation. Microbolometers have applications in gas detectors, night vision, and many other situations.
The primary factors affecting response time and sensitivity of microbolometers are thermal mass and thermal isolation. Microbolometer response time is the time necessary for a detector element to absorb sufficient infrared radiation to alter an electrical property, such as resistance, of the detector element and to dissipate the heat resulting from the absorption of the infrared radiation. Microbolometer sensitivity is determined by the amount of infrared radiation required to cause a sufficient change in an electrical property of the microbolometer detector element. Microbolometer response time is inversely proportional to both thermal mass and thermal isolation. Thus, as thermal mass increases, response time becomes slower since more infrared energy is needed to sufficiently heat the additional thermal mass in order to obtain a measurable change in an electrical property of the microbolometer detector element. As thermal isolation increases, response time becomes slower since a longer period of time is necessary to dissipate the heat resulting from the absorption of the infrared radiation. Microbolometer operating frequency is inversely proportional to response time. However, microbolometer sensitivity is proportional to thermal isolation. Therefore, if a specific application requires high sensitivity and does not require high operating frequency, the microbolometer would have maximum thermal isolation and minimal thermal mass. If an application requires a higher operating frequency, a faster microbolometer may be obtained by reducing the thermal isolation which will also result in a reduction in sensitivity.
To provide multi-spectral imaging capability, two physically separate infrared and visible imaging focal plane arrays have been employed. Images from the two separate focal plane arrays have been fused electronically using hardware and software. However, use of two separate focal plane arrays requires additional space and complicates the structure and circuitry of the imaging assembly.
Wafer level vacuum packaging is an enabling technology for low cost packaging of microelectromechanical systems (MEMS) devices that utilize a vacuum for operation. Such devices include IR bolometer detector arrays, RF resonant devices, and devices with moving parts that may be impeded by the presence of gas in the package. Alternatively, wafer level vacuum packaging is also usefully employed for packaging of devices that utilize a specific atmosphere and or pressure for mechanical damping. Some types of wafer level vacuum packaged MEMS devices are fabricated by attaching a lid wafer of optically transmissive material to a device wafer that includes MEMS devices (e.g., FPA devices) and associated circuitry. In such a configuration, the lid wafer provides an optically transmissive window above the MEMS devices.
MEMS devices that utilize a window that is optically transmissive in the IR spectrum may employ silicon-based material or other IR spectrum-transmissive wafer material for the material of the window of the lid wafer so that silicon-based device wafer and silicon-based lid wafer are thermally matched, i.e., having substantially same temperature coefficients of expansion (TCE). When performing wafer level packaging, little difference between TCE of a lid wafer material and TCE of a device wafer is allowable due to the relatively large diameter of the wafer and the large temperature change required for soldering (e.g., soldering with 80-20 gold-tin AuSn solder), anodic bonding (e.g., at temperatures greater than about 400° C.), and glass frit sealing (e.g., at temperatures from about 400 to about 500° C.).
However, those MEMS devices that require optical transmission in the visible spectrum utilize non-silicon-based window materials (i.e., materials that are primarily composed of a material other than silicon) that are optically transmissive for the visible spectrum. Due to thermal mismatch caused by differences in thermal expansion coefficients (e.g., TCE for silicon is 4.7×10−6/° C., TCE for ZnS=6.14×10−6/° C., TCE for ZnSe=7×10−6/° C.), lid wafers composed of such non-silicon-based visible spectrum-transmissive materials would be under high stress and fracture during bonding which would not be the case for silicon materials. Therefore, devices requiring optical transmission of the visible spectrum (e.g., for purposes of optical I/O) traditionally have employed standard hermetic ceramic or metal packages with an appropriate window bonded onto it, or bonded into a window frame that is then soldered or welded onto the package. However, such a configuration, results in an inherently costly package.
FIG. 20 shows a silicon substrate 2000 that includes CMOS circuitry layers 2030 formed thereon that are configured as individual detector element (or cells) 2060, 2062 and 2064 of an array area 2070 of a conventional focal plane array. In the illustrated embodiment, CMOS circuitry layers 2030 include first CMOS circuit metal layer 2002, second CMOS circuit metal layer 2004, and third CMOS circuit metal layer 2006, each of which are formed during CMOS processing. Third CMOS circuit metal layer 2006 is the top (i.e., last) CMOS circuit metal layer. CMOS circuitry layers 2030 also include first insulator layer 2003 (e.g., planarized oxide layer) between first and second CMOS circuit metal layers 2002 and 2004, and second insulator layer 2005 (e.g., planarized oxide layer) between second and third CMOS circuit metal layers 2004 and 2006, and passivation layer 2007 (e.g., planarized oxide/nitride passivation layer) adjacent third CMOS circuit metal layer 2006. CMOS nitride/oxide passivation layer 2012 is present over the last (or top) metal level layer 2006 in the CMOS circuitry, and input via structures 2016 are opened (e.g., via etching) in the final (or top) CMOS passivation layer to expose input pads 2050 of the top CMOS metal layer 2006.
In the conventional configuration of FIG. 20, a lead metal reflector layer 2014 is formed during post-CMOS bolometer fabrication as a non-CMOS metal layer over top CMOS passivation layer 2012. Also shown in FIG. 20 are electrically conductive metal via (plug) interconnects 2022 that are formed to extend through first insulator layer 2003 between first and second CMOS circuit metal layers 2002 and 2004, and electrically conductive metal via (plug) interconnects 2024 that are formed to extend through second insulator layer 2005 between second and third CMOS circuit metal layers 2005 and 2007. Electrically conductive metal via (plug) interconnects are, for example, TiW or copper.